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The Intellectual Property (IP) Subcommittee's mission is to address the many challenges
in the quality, portability, reuse, verification, integration
and standardization of intellectual property in the semiconductor
industry, particularly as it applies to fabless companies
and their partners.
GSA IPecosystem (IPe) Tool Suite - GSA is creating a Tool Suite to enable more efficient communication between IP vendors, IP integrators/enablers and foundries for IP interaction, an area critical for design success. It involves the development and deployment of useful applications to the industry, aiding in the communication of key business and technical information between parts of the supply chain. Success criteria includes bringing engagements down from months to days and improving the confidence level (i.e., lowering the risk) in business decisions made around IP.
Risk Assessment Tools within the Suite (v4.003) include:
- Hard IP Quality Risk Assessment Tool - Features a set of questions that every integrator needs to ask to understand what the IP includes and evaluate its risk assessment prior to determining which IP to purchase based on a chosen risk profile.
- Licensing - Features a set of best practices questions that every integrator asks to understand the IP when evaluating a licensing transaction.
Future Tools include:
- Technology – Will feature a set of questions that focus on PDKs, Models, etc. to determine the technological readiness of the IP under evaluation.
- Manufacturability – Will feature a set of best practices questions that identifies the risk profile to ensure the chip will manufacture at yield in a timely manner at the lowest possible cost.
IPecosystem Tool Suite v4.003 -
This robust business tool, conveniently packaged in one application provides IP vendors and integrators/enablers with the most efficient and effective method of evaluating IP. Version 4.003 includes Hard IP Quality and Hard IP Licensing.
The Current State of Semiconductor Intellectual Property (SIP) Licensing White Paper - A document identifying and summarizing common issues encountered in third-party IP negotiations for use by third-party IP integrators.
Understanding The Semiconductor Intellectual Property (SIP) Business Process: Finding, Evaluating And Licensing Commercial SIP - An educational document detailing the business and legal issues associated with identifying, evaluating and licensing SIP. The Understanding the SIP Business Process Presentation supplements this document.
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Technology*
The Technology Working Group is developing a series of questions for the foundry to communicate the abstract answers at critical junctures for technology information exchange with semiconductor customers. The group will leverage the work performed in the MS/RF Subcommittee on Process Design Kits (PDKs) and SPICE Model Checklists to develop the Tool for the IPecosystem Tool Suite.
Meetings: Contact Lisa Tafoya for more information or to join.
Chair: Raminderpal Singh
Hard IP Quality*
The Hard IP Working Group, consisting of IP integrators, vendors and foundries, developed a Hard IP Quality Risk Assessment Tool for third-party IP and reuse. After many regularly held working meetings during the Hard IP Risk Assessment Tool development phase, the group's meeting activity has slowed to discussing features and enhancements for newer versions. The group is continuously working to make the tool easier and more user-friendly as it evolves and is adopted worldwide. Download
Meetings: Occasional meetings are all conducted via Web conference and teleconference, as needed.
Chair: Raminderpal Singh
Licensing*
The Licensing Working Group completed their objective by developing a set of best practices questions that every integrator should ask to understand the IP when evaluating a licensing transaction with a vendor. Download
Meetings: Occasional meetings are all conducted via Web conference and teleconference, as needed.
Chair: Raminderpal Singh
Manufacturability*
The Manufacturability Working Group will develop a set of questions that identifies the risk profile to ensure the chip will manufacture at yield in a timely manner at the lowest possible cost.
Meetings: Contact Lisa Tafoya for more information or to join.
Chair: TBD
GSA members working with IP integration, quality, portability,
reuse, verification and other IP-related issues, are encouraged
to get involved.
Join
This Subcommittee – By signing up, you will be
added to a distribution list and receive upcoming meeting
notifications.
For more information, contact:
Lisa Tafoya, GSA
(T) (972) 866-7579 Ext. 116
(E) ltafoya@gsaglobal.org
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Indicates subcommittee