GSA Business Tools

Foundry Process Qualification Guideline

In 1999, GSA released a 0.25-micron technology specific guideline. The 0.25 micron SFPQ Program, initiated in 1997, was designed to standardize the foundry process qualification by providing the industry's most comprehensive test chip. The proposed test chip contained all the necessary process qualification components, including an SRAM, logic, qualified library and IP elements, reliability physics tests, minimum electrical parametric tests, process evaluation and SPICE modeling test structures. Following the manufacturing process, each certified foundry agreed to adhere to the official process qualification and reporting guidelines.

For technology generations beyond 0.25-micron, the effort shifted toward the drafting of a guideline for the qualification of generic silicon-based CMOS technologies. The new guideline relies to the fullest extent possible on existing JEDEC and other standard methods. The required tests are described in sufficient detail to provide enough understanding of the expected output, but proper implementation of the various qualification tests requires the user to refer to the full text of the test procedure, as described in the relevant standard. Rather than develop a custom test chip, the guideline defines test structure requirements in accordance with existing industry standards.

The guideline was a joint effort of GSA and the JEDEC. It went through numerous reviews and two formal JEDEC ballots. In 2002, FSA, now GSA, and JEDEC announced the release of the Foundry Process Qualification Guideline, which is used by numerous foundries and fabless companies today.

Deliverables

• JP001 Questionnaire Results Summary - Aug. 2004 (198KB)
• JEDEC/FSA JP-001 Aug'02.pdf (276KB)

For more information contact:

Kristen Pillans, GSA
(T) (972) 866-7579
(E) kpillans@gsaglobal.org