Meet the Speakers

Joe Abler

Joe Abler is a Senior Technical Staff Member in the IBM Systems and Technology Group at Research Triangle Park, North Carolina. Joe is a member of IBM's Common Platform Strategy team, driving a technology collaboration of IBM, Chartered Semiconductor, and Samsung Electronics. Joe's responsibility is to develop and strengthen alliances with industry IP and EDA providers to build a comprehensive ecosystem enabling the Common Platform's base technologies and delivering client solutions. He joined the IBM Microelectronics Division in 1999, bringing to the team over 20 years of experience in networking, storage, and consumer related technologies.

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Rob Aitken

Robert C. Aitken is an R&D Fellow at ARM. His areas of responsibility include low power design, library architecture, and design for manufacturability. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He has published over 70 technical papers, and has twice received the best paper award from the International Test Conference. He holds a Ph.D. degree from McGill University in Canada. Dr. Aitken is a senior member of the IEEE, and served as general chair of the 2005 International Test Conference.

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William Billowitch

William Billowitch is a Director of Marketing at Cadence Design Systems where he manages the IP & EDA alliance partnership programs comprising over 225 member companies. Before assuming his current position, Billowitch was Sr. Customer Marketing Manager for the Storage division of Agere Systems (now LSI Corp). Mr. Billowitch has significant experience in the development of intellectual property in embedded software, digital, mixed-signal and verification IP having served as Sr. Technical Manager of Agere's IP Design Reuse & Development organization; Director of IP Development at design services firm Intrinsix Corp; CEO of The VHDL Technology Group (acquired by Intrinsix) and Exec VP Mktg at Quadtree Software Corporation (acquired by Logic Automation/Synopsys). Billowitch served on the board of the Virtual Socket Interface Alliance (VSIA) and led the technical direction of the Quality IP (QIP), was Technical Director of the Cadence led VITAL Initiative (now IEEE 1076.4), as well as chair of the IEEE 1164 VHDL interconnection standard. Billowitch graduated with a BSEE from Lehigh University in Bethlehem, Pa.

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Dennis Brophy

Dennis B. Brophy is director of strategic business development at Mentor Graphic Corporation. He is also volunteer vice-chairman and past chair of Accellera, an electronic design automation standardization group. Dennis has been in the electronic design automation industry for the past 28 years. He was first with Hewlett-Packard for five years, and then joined Mentor Graphics where he has held several positions the past 23 years. He is a member of the IEEE Standards Association (SA) Board of Governors (BOG) and a vice chairman of the IEEE SA Corporate Advisory Group (CAG). He is secretary of the IEEE P1800 SystemVerilog Working Group, secretary of the IEEE 1666 SystemC Working Group and participates in the IEEE P1801 Low Power Working Group. Dennis is also a member of the American National Standards Institute (ANSI) and is a member of the United States National Committee for EDA standards. He is a co-convenor of IEC TC93 WG2. Dennis received a Bachelor of Science degree from the University of California at Davis in electrical engineering and computer engineering in 1980.

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Ron Burns

Ron serves as General Manager, Semiconductor and Systems Solutions. Ron's business career spans 20 years of Semiconductor, Electronic Design Automation, and Embedded Systems experience. Most recently, Ron served as VP, WW Sales Teja Technologies, a new venture focused on multicore embedded systems, recently sold to ARC. Prior to Teja, Ron was the VP-Marketing for Axis Systems, a technology leader in HW/SW Co-Verification Solutions.

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Dave Bursky

Dave Bursky, currently the Semiconductor Technology Editor for Chip Design Magazine, has over 35 years of experience as an editor, working for publications such as Electronic Design and EE Times prior to joining Chip Design. Prior to his editorial career he also worked as an engineer for the U.S. Army. In 2005 he was inducted into the Communications Society Hall of Fame for Lifetime achievement at the City College of New York. Dave is one of several Electronic Design editors awarded the Jesse H. Neal award for Editorial Excellence. In 1988 he was described by the San Jose Mercury News as one of the 100 most influential people in Silicon Valley. He has also taught digital logic technology at the former RCA Institute in New York City. He has also authored six books on topics ranging from personal computers to semiconductor memories. Dave holds both Bachelor's and Master's degrees in Electrical Engineering from the City College of the City University of New York (1971 and 1973, respectively).

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John Chilton

Since 2006 John has served as Senior Vice President at Synopsys responsible for Marketing, Strategy, and Corporate Development. In that capacity, he manages Strategic Planning, Marketing, and M&A. From 1997 to 2006 he served as General Manager for Synopsys' IP, Services, and Systems level businesses. John joined Synopsys in 1995 with the acquisition of Arkos Design, an emulation company he co-founded and served as CEO. Prior to Arkos, John served as CEO of EMS, an RFID company which he co-founded in 1985, and Datalogic USA, the US subsidiary of a leading European automatic identification company which acquired EMS. John has a MSEE from USC and a BSEE from UCLA and holds four patents.

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Ron Collett

Mr. Ronald E. Collett, President and CEO of Numetrics Management Systems, has spent over 25 years in the electronics industry, where he has held positions in executive management, engineering, marketing and sales. He founded Collett International, Inc. in 1992 and also spent several years at the Dataquest division of the Gartner Group, where he oversaw the firm's activities in the areas EDA, application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). Mr. Collett is recognized as the first to identify and call the industry's attention to the now well-known "design productivity gap." He has published over 100 articles on the design of integrated circuits (ICs) and electronic systems. He holds a Bachelor of Science degree in electrical engineering from Drexel University and a degree in law from Santa Clara University, and he is member of the California Bar.

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Dr. Wayne Dai

Wayne Dai is the founder, Chairman, President and CEO of VeriSilicon Holdings Co., Ltd. He was the Co-Chairman and Chief Technology Officer of Celestry Technologies, Inc., which was acquired by Cadence Design Systems in 2002. Prior to that, he was the founder, Chairman, and CEO of Ultima Interconnect Technology, Inc., one of the predecessor companies to Celestry. He was the founding Chairman of the IEEE Multi-Chip Module Conference and the founding Chairman of IEEE Symposium on IC/Package Design Integration. He was an Associate Editor for IEEE Transactions on Circuits and Systems, and an Associate Editor for IEEE Transactions on VLSI Systems. He has published over 100 papers in technical journals and conferences and received the Presidential Young Investigator Award from the President of United States in 1990. In the year of 2005, Dr. Dai was elected as one the top ten venture-backed entrepreneurs in China, and elected as one of the 2005 top ten talents of science and technology in China. And just the year of 2007, Dr. Dai won The Ernst & Young Entrepreneur of the Year China 2007. Wayne Dai received his B.A. degree in Computer Science and his Ph.D. degree in Electrical Engineering, both from the University of California at Berkeley. He was a Professor in the department of Computer Engineering at the University of California at Santa Cruz.

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Nitin Deo

Nitin Deo has enjoyed a broad range of industry experience, including design, product marketing, sales and business development. Before joining Cadence, Mr. Deo was vice president of marketing and business development at Clear Shape Technologies, which was acquired by Cadence in 2007. Prior to Clear Shape, he held a similar role at Ponte Solutions Inc. Mr. Deo was also a marketing executive at Moscape, Inc. After the pre-IPO acquisition of Moscape by Magma Design Automation, Inc., he became vice president and general manager for Japan operations and later, vice president of marketing and business development. Previously, he worked at Fujitsu and Philips and was at Synopsys, Inc. for five years as group director of marketing and business development. He started his career doing ASIC design at Mitsubishi Semiconductor in Japan. He has a BSEE from the University of Mysore in India, an MSEE from Virginia Tech and an MBA from San Jose State University.

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Marc Greenberg

Marc Greenberg is the Director of Technical Marketing for the IP products group at Denali Software, Inc. A Masters' graduate from the University of Edinburgh in Scotland, Marc's career includes 10 years at Motorola in IP creation, IP management and SoC Methodology roles in Europe and the USA. Marc has been working with Denali's Databahn memory controller since joining Denali in 2003 and has presented at many conferences including ASIC'98, IP'99, ARM Developers' Conferences and Denali's SoC Seminars.

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Oliver Gunasekara

Oliver has over 16 years of experience in semiconductor and mobile management, marketing, business development, sales and M&A. His past tenures include VP Corporate Business Development (USA), Global Director of Mobile Solutions (UK) and Mobile Business Development Manager (Japan) at ARM. Oliver selected, justified and executed ARM's acquisition of Falanx Microsystems; he owned the vision, direction and strategy of ARM's wireless team - resulting in over 90% market share in mobile handsets - and was founder and board member of the MIPI Alliance Inc. Oliver joined ARM as an FAE in 1995 when the company was a 60 person startup. His contributions were key to the company’s IPO. Prior to ARM, he worked as an embedded software engineer for Crossfield Electronics (UK), and as an FAE in analog wireless chips for Manhattan Skyline (UK). Oliver holds a Bachelor's degree with honors in Electrical and Electronic Engineering from the University of Greenwich, London, UK.

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Robert Heaton

Robert graduated from the University of Surrey (UK) in 1979. During the early 1980's, he ran the VLSI Group at Acorn Computers, developing the ARM 32-bit RISC processor chipset. During the 1990's, Robert ran West Coast engineering for Standard Microsystems and founded Obsidian Technology. In recent years he has focused on 1GBase-T, 10GBase-T DSP and mixed signal design. Robert has several patents in the areas of Ethernet and data compression.

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Ming C. Hsu

Ming Hsu is VP of Worldwide IP Support at UMC. In this position, he is responsible for supporting UMC customers SoC design requirements, including IP (Intellectual Property) development, IP Management, design support for Customer Engineering, EDA tools, and design verification. Prior to joining UMC, Mr. Hsu held various management and engineering positions at Systonics, Clear Logic, Lattice Semiconductor, and IDT. He received a BS degree in Materials Science Engineering from National Tsing Hua University in Taiwan, and an MSEE from University of Southern California.

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Ana M. Hunter

Ana Molnar Hunter is vice president of Technology for Samsung Semiconductor, Inc.'s System LSI foundry business. Leading the US business development team, Hunter is responsible for Samsung's foundry customer activities in North America. She is also responsible for setting the strategic development direction of the North America foundry business. Prior to joining Samsung, Hunter spent the last 15 years working in the semiconductor foundry industry in various positions as a consultant, vice president of U.S. operations for Communicant Semiconductor Technologies AG, Germany, and vice president of EDA and customer services for Chartered Semiconductor, Inc. She holds a B.S. in chemistry from Duke University.

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Charles Janac

K. Charles Janac is an entrepreneur with over 20 years of experience of building new technology companies. He is currently the Chairman, President and Chief Executive Officer of Arteris Inc. - pioneering a market for Network on Chip (NoC) interconnect IP and Tools for on-chip communications inside complex semiconductor chips. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a NYSE traded $1.2B revenue company. Subsequently, he served as CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California and has worked for Exxon Chemical Company in technical and sales positions. Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. He holds one patent in polymer film technology. Charlie currently reside in Los Altos Hills, California.

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Joachim Kunkel

Joachim Kunkel is the Vice President and General Manager of the Solutions Group at Synopsys, Inc. In that capacity, he manages the business units responsible for Synopsys DesignWare intellectual property (IP) and system-level design. Prior to joining Synopsys in 1994, Joachim was a managing director of CADIS GmbH, a company he had co-founded in 1989 in Aachen, Germany. CADIS GmbH focused on the development of system level design tools for digital signal processing and providing specialized design services for wireless communication systems. From 1984 to 1989, Joachim was a research assistant at the Aachen University of Technology's Lehrstuhl fuer Elektrische Regelungstechnik, where he conducted research in the area of system level simulation techniques for digital signal processing, with special emphasis on parallel computing. Joachim holds an MSEE from the Aachen University of Technology, Aachen, Germany.

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Tom Lantzsch

Thomas Lantzsch joined ARM in December 2006 as the Vice President of Marketing for the Physical IP Division. Mr. Lantzsch has been a senior business leader for over 25 years at both Fortune 500 companies and early stage startups including the Chief Executive Officer of StarCore in Austin, Texas. He spent 13 years with Motorola in Vice President positions of sales, marketing and operations in four countries. He began his career with Texas Instruments in Dallas, Texas. He has built a reputation for his ability to identify new opportunities of competitive advantage and developing strategies to capitalize upon them through the definition of new products, services, organizations or the use of technology. He frequently lectures on business strategy and trends at the McCombs School of Management at the University of Texas, investor conferences and industry events. Mr. Lantzsch completed his BSEE at Michigan State University and MS finance from the University of Texas in Dallas.

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Dr. Jaushin Lee

Dr. Lee is the founder, CEO, and president of Imera Systems. He has over 16 years of R&D and management experience in networking and computing engineering. Before founding Imera Systems, he managed the Cisco Network Search Engine (TCAM) and high-speed SRAM programs and was responsible for the technology strategy behind interacting with the world's largest semiconductor vendors. Prior to Cisco, Dr. Lee held engineering management positions with Terawave Communications and Silicon Graphics, Inc. and was an assistant professor at the University of Virginia. Dr. Lee holds a Ph.D. in EECS from the University of Illinois at Urbana-Champaign, MS in EE from Columbia University, and BS in EE from National Taiwan University. He has published 15 international conference and journal papers and filed six US patent applications and numerous provisional patent applications.

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Lars Liebmann

Dr. Liebmann came into Design for Manufacturing (DfM) with a background in advanced lithography where he spent the first thirteen years of his career developing and implementing layout manipulation solutions for optical proximity correction and resolution enhancement techniques which lead him to explore the domain of lithography friendly layouts. His current interests include the use of ultra-regular layouts as a means of preserving profitable CMOS scaling for the diverse set of logic products that define IBM's technology nodes. Dr. Liebmann holds over 60 patents and has published over 40 papers, he currently serves as the chair of the Technical Steering Group of Si2's DfM Coalition, formed to define an open-standard IT infrastructure against which DfM applications can be integrated. A member of Solid State Technology's Editorial Advisory Board, he is a program committee member of SPIE's "Design for Manufacturability through Design-Process Integration" conference and has taught several short courses on DfM at various technical venues.

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John Maneatis

John Maneatis is TCI's co-founder, President, and Chief Technologist. He holds a B.S. degree in Electrical Engineering and Computer Science from U.C. Berkeley, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. John brings 20 years of experience to TCI in analog and digital circuit design and is world renowned for his work in the area of Phase-Locked Loop design. Prior to co-founding the company, he was a lead circuit designer at Silicon Graphics in their advanced microprocessor design group.

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Walter Ng

Walter Ng reports to the Senior Vice President of Technology Development and is responsible for identifying, developing and executing customer and partner alliances that advance the adoption of Chartered's solutions for the leading-edge and mainstream technology nodes. Walter has led the company's collaboration with IBM to define the strategy and implementation of the solutions and third-party network for the industry's first common design enablement platform at 90 nanometer (nm) and 65nm while currently driving 45nm and setting strategy for 32nm. Previously, Walter served as senior director of design solutions and was responsible for driving and managing Chartered's relationships with third-party EDA and IP partners. Walter has been in the electronic design and EDA industry for nearly 20 years. Prior to joining Chartered, Walter was Director of Business Development and Asia Pacific Operations with Sequence Design. From 1994 to 1999, Walter worked with Cadence Design Systems, where he held positions in strategic marketing and numerous roles in applications engineering, consulting services, sales support and marketing. Previously, he has held various senior design and test engineering positions in Raytheon's Equipment Development Labs. Walter holds a B.S. in Electrical Engineering from the University of Massachusetts, Amherst, and an M.B.A from the University of Massachusetts, Boston.

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Martin Niset

Martin Niset is the Product and Test Engineering Manager for Virage Logic Nonvolatile Memory group (formerly Impinj IP division). Previously Martin worked in embedded flash development at Freescale Semiconductor. Martin's specific areas of expertise involve nonvolatile memory test methodologies, reliability testing (including automotive requirements), and qualification testing. Martin holds multiple patents on nonvolatile memory technology and techniques.

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Dipesh Patel

Dr. Dipesh Patel is currently Vice President of Engineering at ARM's Physical IP Division and is responsible for all IP development activities in the division. From August 2006 to January 2008, he was Vice President of Technology for the Physical IP Division and was responsible for the advanced products developed in the division. From September 2003 to August 2006, as Director of Research at ARM, he led ARM's research activities based in Cambridge, UK. He joined ARM in 1997 and has worked primarily in System on Chip (SoC) related activities. He was a key member of the team that developed the Intelligent Energy Manager (IEM) technology and was responsible for transfering that technology into product development. His primary research interests are in Low Power SoC environments. Dr. Patel received a PhD in Electronic Engineering from Loughborough University in the UK.

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Kalar Rajendiran

Kalar Rajendiran is the Senior Director of Marketing for eSilicon Corporation, where he is responsible for the company's product marketing, marketing operations and semiconductor IP strategy. Prior to joining eSilicon in 2000, Rajendiran has held several senior engineering and marketing management positions with National Semiconductor, LSI Logic and Larsen & Toubro. He holds a BE in Electrical Engineering from Anna University, an MS in Computer Science from Texas Tech University, and an MBA from Santa Clara University.

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Glenn Raskin

Mr. Glenn Raskin is a Director of Program Management at QUALCOMM CDMA Technologies (QCT). Mr. Raskin began his career at QUALCOMM in 2004 working on transforming the largest Fabless Semiconductor Companies Supply chain from Turn-key to an advanced direct business model. As of 2006 Mr. Raskin has been responsible for the Program Management of Systems Architecture, Wired Peripheral IP, and advanced VLSI Technologies for QCT. His work focuses both on coordinating internal development and partnering with external IP and Technology partners. Prior to joining QUALCOMM, Mr. Raskin held design, product and technology management engineering roles with Motorola/Freescale Corp in Phoenix Arizona. Mr. Raskin holds Masters and Bachelors degrees in Materials Science & Engineering from Cornell University.

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Craig Rawlings

Craig Rawlings is Director of Marketing at Kilopass Technology. He has more than 15 years of experience in the semiconductor industry. Prior to joining Kilopass, Craig was a VP of Sales at Resilience Corporation, and he has held management positions at Hewlett-Packard and Actel. Craig holds a B.S.E.E. degree and a Masters of Business Administration from Brigham Young University.

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Emmanuel Riou

Emmanuel's business career spans 14 years of work in RF IC design, WLAN applications, GSM and Bluetooth. He worked on the design of transceivers for GSM and receivers for pagers, in the early part of his career. He was part of the team which designed the first Zero IF transceiver for WLAN applications (802.11b). With Airgo Networks, Palo Alto CA, he worked on the design of the first MIMO transceiver chip for WLAN 11a/b/g. Since 2005, he has been a part of Wipro NewLogic, where he currently holds the position of RF Engineering manager, in charge of the development of IPs mainly for BT and WLAN applications.

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Gary Ruggles

Gary Ruggles is Director of Worldwide Sales for the Snowbush IP Division of Gennum. He has over twenty years of experience in the field of electronics and integrated circuit design and has spent the last ten years leading the development, sales and marketing of high-speed serial link (SerDes) IP. Prior to Gennum, Gary served as Director of Marketing and Business Development and Director of Worldwide Sales for PHY Products at ARM where he grew PHY revenues over 500% and coordinated activities across the sales, marketing and support organizations. Previously, he was Program Manger at Cadence Design Systems in 1998, where he managed the design of Cadence's first CMOS-based gigabit Ethernet transceiver. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University where he taught courses in Solid State Physics and VLSI Processing and Design and gave lectures for the National Technological University. Dr. Ruggles holds BS, MS and PhD degrees in Electrical Engineering from Penn State University.

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Kamalesh Ruparel

Kamalesh Ruarel brings more than 22 years of semi-custom integrated circuit (IC) ecosystem experience to his role as Virage Logic's Vice President and General Manager of Application Specific IP (ASIP) Solutions and Silicon Technology. In this role, Ruparel is responsible for driving the company's ASIP business (the company's functional IP product line established through the acquisition of Ingot Systems in August 2007) and the silicon validation of all Virage Logic products including test chip development, test chip characterization and silicon reports. Previously he spent approximately ten years at Cisco Systems, most recently serving as director of engineering for the ISBU ASIC-COT Engineering in the Datacenter, Security & Switching Technology Group. Ruparel's experience also includes management positions at Apple Computer and senior engineering positions at Vertex Semiconductor, and Texas Instruments. Ruparel holds a BS in electrical engineering from the University of Texas at Austin and an MS in computer science from the Southern Methodist University in Dallas.

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Warren Savage

Prior to founding IPextreme, Mr. Savage created and ran the Star IP Program at Synopsys, where he provided an IP brokering function for major semiconductor companies. Prior to that, Mr. Savage was head of the Synopsys DesignWare engineering organization, where he introduced many design practices and quality measures, which eventually became part of the Reuse Methodology Manual, a seminal book on Intellectual Property design. From 1982-1995 he worked for Tandem Computers, and there developed an interest in advanced design methodologies around high reliability design. Mr. Savage began his career at Fairchild Semiconductor developing semiconductor test equipment. Mr. Savage is a well-known and published authority in the field of semiconductor intellectual property. Mr. Savage has a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine University.

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David Schwan

David Schwan is a CAD and Layout Manager for RFMD and works in the Multi-Market Product group (formerly Sirenza Microdevices). He is responsible for all tool support for the MPG division; which includes Analog, Digital, and RF tools; System level design, front end design, and back end design. He is the author of numerous papers in CAD methodology and IP. He has two patents pending. He is a member of the GSA mixed-signal subcommitte, and is an active participant in the GSA IP ecosystem. He is an IEEE member.

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Jordan Selburn

Jordan came to iSuppli with decades of extensive experience in ASIC, Programmable Logic and semiconductor intellectual property (IP) analysis, product marketing, and engineering development. Prior to joining iSuppli, Jordan served as the Director of Product Marketing for Amphion Semiconductor. Prior to his tenure with Amphion, Jordan was the Principal Analyst for ASIC and IP at Gartner Group/Dataquest and as such was responsible for the evaluation and analysis of semiconductor IP as well as the ASIC and programmable logic markets. Marketing Manager and Product Line Manager positions at LSI Logic preceded his employment at Gartner Group/Dataquest. Before LSI Logic, Jordan was an ASIC Technology Manager and a Corporate Applications Engineer at Valid Logic Systems/Cadence Design Systems and was also associated with Agilent/EEsof, Inc. and Harris Corporation in various engineering capacities. Jordan holds a Masters of Science in Engineering Economic Systems from Stanford University in addition to an MBA with distinction from Santa Clara University and a BSEE with honors from the University of Michigan.

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Raminderpal Singh

Raminderpal Singh received his Bachelors of Engineering in 1991, at Imperial College, London University. He then spent a year as a venture capitalist with 3i plc (UK). Dr. Singh received his Ph.D. in Electrical Engineering (1997) from Newcastle University (UK). He then worked for Cadence Design Systems (1997-2001). In March 2001, Dr. Singh joined IBM's RF/Mixed-Signal Design Kit Group (Burlington, VT), where he was Senior Engineering Manager. In 2004, he moved to IBM's Fishkill location for the 300mm fabrication facility. Currently, Dr. Singh is a business analyst covering the semiconductor industry, in IBM's Corporate Market Intelligence team. Dr. Singh has authored and co-authored numerous technical publications, including 2 books and several chapters for books. In 2003, Dr. Singh was named by EETimes as one of the top thirteen Influencers in the Semiconductor industry. Additionally, he has been leading industry working groups for close to ten years, starting with the industry's first signal integrity standard developed at the VSIA, and is currently driving the IPe Ecosystem series of projects at the GSA.

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Ann Steffora Mutschler

Ann Steffora Mutschler is a Senior Editor for Electronic News and Electronic Business — now part of EDN. She writes daily news, insightful feature articles, and "The Sandbox" blog, keeping her finger on the pulse of the leading chip providers, as well as the design and manufacturing tool providers. Her main focus currently is semiconductor manufacturing and everything that entails. Ann first joined Reed Business Information when it was Cahners Publishing Company, in 1997, as an associate editor with Electronic Business, followed by two years at Electronic News as a Senior Editor. Ann rejoined the company as a contract writer for Electronic News in 2003, and as a Senior Editor for Electronic News and Electronic Business in 2006. Between her jaunts with the company, Ann worked for a few years in public relations (for perspective on the industry) and also as Managing Editor for EDACafe.com and the now-defunct EDAVision.com. Prior to 1997, Ann worked for a number of high-tech publications and her articles have appeared around the world.

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Lisa Tafoya

Lisa Tafoya is the vice president of global research for GSA. Tafoya is responsible for GSA's market intelligence, surveys and publications, and serves as executive editor of GSA Forum, the premier industry journal exclusively targeting fabless, IDM and outsourcing markets. She also manages all GSA subcommittees which address industry challenges with solutions-based deliverables such as standards, quality checklists and guidelines. Tafoya has spent 15 years in market research, consulting, project management and marketing communications. She earned a bachelor's degree in marketing from Southern Methodist University.

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Ken Tallo

Ken Tallo is director of Intel's External IP and Virtual Platforms Group. He is responsible for Intel's long term silicon IP strategies, as well as establishing IP procurement, storage, and tracking processes. As part of his dual Intel Corporate wide charters, he is also responsible for driving next generation Electronic System Level (ESL) design methodologies targeted at early software development and architectural exploration. During his 9 years with Intel, he has held several design and senior management positions, focused on growing Intel's emerging SoC businesses. Ken has over 20 years experience in Design Automation, IC Design, Test and post-Si validation. He was recently elected Chairman of the Open SystemC Initiative (OSCI) where he with other semiconductor companies have been proactively working with the EDA industry to quickly deploy ESL standards, tools, and methodologies. Ken holds a B.S. degree in Electrical Engineering from Louisiana State University.

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Mahesh Tirupattur

Mahesh Tirupattur is responsible for world-wide business and engineering operations for Analog Bits, Inc. In this role, he handles partnerships, licensing, and joint-ventures of Analog Bits' IP to semiconductor manufactures, fabless ASIC/SoC designers and system houses. He also manages channel partnerships with semiconductor fabs, EDA companies and ASIC suppliers. Marketing functions include technical product marketing, product deployment strategy and corporate marketing. Prior to Analog Bits, Mr. Tirupattur was Co-founder and Vice President of Sales for Virtual Silicon Technology. Previously, he served as Director of Product Marketing at Aspec Technology, Field Applications Manager at Epic/Synopsys, and held a technical staff position with Sun Microsystems. Mr. Tirupattur received his M.S. degree in Electrical Engineering from Arizona State University.

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Adam Traidman

Adam Traidman is Group Marketing Director of the Chip Planning Solutions organization within Cadence Design Systems. He recently joined through the acquisition of Chip Estimate Corporation, where he served as President & CEO for the past four years. Prior to that, Adam ran North America West sales for Hier Design, an EDA company focused on floorplanning solutions acquired by Xilinx in 2004. Adam had previously held a variety of technical and management positions at in deep sub micron IC implementation at Texas Instruments, Adaptec and the NASA Jet Propulsion Laboratory.

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Katty Van Mele

Katty Van Mele joined Sarnoff Europe, a silicon IP ESD design solutions provider, in 2006, where she focuses on the North American and Asian markets, in particular on the fabless and foundry industry. She fostered several new foundry alliances and pioneered new application markets. As Director Strategic Alliances she advocates flexible and cross-boundary cooperation within the semiconductor supply chain, and is an active participant in the GSA IP Ecosystem Quality initiatives. Katty's 15+ years of business experience span the globe, with business development appointments focusing on North America and Asia-Pacific strategic cooperation at European and Chinese technology companies. She was instrumental in setting up several technology joint-ventures within the EU-China framework for industrial and consumer electronics applications. Katty Van Mele earned her M.A. in East Asian studies from the Catholic University Leuven, Belgium and a double postgraduate degree in international relations and East-S.E. Asian economy from The Johns Hopkins University - SAIS in Bologna, Italy and Washington, D.C.

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Massimo Verita

Massimo Verita has over 20 years of experience in the IC and Semiconductors industry, where he assumed a variety of roles in Engineering, Customer Engineering and General Management of business units in the Wireless and Consumer markets. Prior to joining eASIC, Massimo was Vice President and General Manager, Consumer Custom Solutions at LSI Logic, where he had responsibility for high volume ASIC designs in the Consumer market. Previously he held various senior management positions at LSI Logic, including the Processor Cores unit, which drove Intellectual Property licensing and strategy for the company. He started his career as Applications Engineer at AT&T Microelectronics (today's Agere Systems). Massimo holds a degree in Electrical Engineering (MsEE) from the University of Trieste, Italy.

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Ron Wilson

Ron Wilson, EDN's executive editor, boasts a checkered career reaching back to the dawn of medium-scale integration. As a design engineer for Tektronix, Inc. he developed bus interfaces and participated in processor- and graphics-engine architecture and design, as well as evaluation engineering and software-driver development. Later an exile from engineering, Ron wandered through the realms of training and marketing before landing happily in the editorial world, first with Computer Design Magazine in the mid-1980s. From there he moved to CMP Media, where he wrote for EE Times and was briefly involved with ISD Magazine. His primary interests are system design based on highly-integrated ICs, the interaction of chip and software engineering and the future of design practice in the increasingly global electronics community.

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Kurt Wolf

Kurt A. Wolf is director of the Library & IP Management Division reporting into TSMC's Design and Technology Platform organization. He is responsible for Library & IP Partner Management and Development & Qualification programs at TSMC. Previously Kurt was director of marketing at TSMC North America, responsible for library marketing and development programs. Prior to joining TSMC, Kurt worked at Advanced Micro Devices, as director of technical marketing Flash memories. Kurt has an MBA from Santa Clara University and a BSEE from the University of Michigan.

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Dr. Yervant Zorian

Dr. Yervant Zorian has served as Virage Logic's Vice President and Chief Scientist since joining the company in 2000. Prior to that, Dr. Zorian served as a Distinguished Member of the Technical Staff at Lucent Technologies, Bell Laboratories and Chief Technical Advisor to LogicVision. Dr. Zorian also serves as the Vice President of the IEEE Computer Society for Conferences and Tutorials and is the Editor-in-Chief Emeritus of IEEE Design & Test of Computers. He founded and presently chairs the IEEE 1500 standardization working group for embedded core test, and has authored more than 250 papers and four books. Dr. Zorian has received a number of best paper awards, is an honorary doctor of the National Academy of Sciences of Armenia, is a Fellow of the IEEE, and is the recipient of the 2005 IEEE Industrial Pioneer Award. Dr. Zorian received an MSc degree from the University of Southern California, and a Ph.D. from McGill University.

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