System-in-package ConferenceJanuary 23-24, 2007

SiP technologies have great promise for function, cost, and time-to-market to the electronic systems and device communities. The increased complexity requires cooperation and collaboration along the supply chain, i.e. between device designers, packaging designers, test engineers and manufacturing.

The SiP Conference will focus on:

  • Market and product opportunities through SiP technologies
  • Knowledge and network for SiP implementation in the fabless environment
  • Challenges for the supply chains involved in design, test and manufacturing of SiP products
  • Bringing together all the players in the supply chain to articulate issues and define strategies to tackle them

Published articles on the SiP Conference:

"Navigating SiP in the Fabless Environment"
Tuesday, January 23-24, 2007
8:00am to 5:00pm
Doubletree San Jose
2050 Gateway Place
San Jose, CA
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Featured Topics

Day One:

 

Tutorial Tracks

  • SiP Drivers, Applications, and Issues
  • SiP Co-Design Flow / Modeling & Simulation

  • 3D Intefration at Wafer Level

  • Design for Test in the SiP Environment

 

Keynotes

  • SiP Application and Business Trends
  • SiP Technology Overview

 

Invited Presentation: Methodologies & Lessons Learned

  • Small Form Factor Applications
  • High Performance Applications
  • Mobile Product System Integration Applications

 

Day Two:

 

Keynotes

  • SiP & Systems Integration - A Perspective from ITRS
  • SiP Approach in Samsung

 

Three Panel Discussions with Industry Expert

  • User Vision for Future Co-Design, Simulation & Test Environment
  • Co-Design/Simulation Tool Vision/Roadmap, to Align Tool Supply Chain Development with the SiP Design Requirements
  • SiP Test Methodology, the Need for DFT, Debug Capability and Improving Yields

 

 

FSA SiP Market and patent analysis

 

"This report is a valuable reference for FSA members engaged in plans for SiP technology and products including chip design, manufacturing, packaging, testing and module/system houses, since the report highlights market and patent information for acquisition and applications."     

 

- Dr. Shyi-Ching (Sebastian) Liau, co-chair of FSA's SiP Subcommittee and project director of Electronics and Optoelectronics Research Laboratories (EOL) at ITRI

 

Learn More

Why Attend
  • Knowledge of directions and trends for SiP in the Fabless community
  • Understand state of the art of SiP co-design tools and SiP DFT strategies across FSA product and supply chain community
  • Enable solutions for the FSA community
    • Stimulate partnership developments across the supply chain
    • Stimulate SiP co-design tools and DFT methodologies in suppliers' roadmaps
  • Understand future roadmaps
  • Tighten technical linkages across the supply chain
Who Should Attend

All IC industry professionals, including who need to use SiP and want to learn more about it.

Pricing

FSA Members:  $199
Non-members: $299

Sponsors
Ansoft ASE Group Cadence
   
True Circuits Simucad MagnaChip Cadence Design Systems, Inc. TSMC Dongbu